1. Field of the Invention
The present invention relates to a flash memory device. More particularly, the present invention relates to a flash memory device having a split gate and a method of manufacturing the same.
2. Description of the Related Art
Non-volatile memory devices are now widely used in various fields because of an ability to electrically store and erase data, and to retain data even without power.
A flash memory device having a split gate is a type of non-volatile memory device, and has a structure in which a floating gate and a control gate are separated. The floating gate is electrically isolated from the exterior and stores information using the characteristic that the current of a memory cell varies according to injecting (writing) electrons into the floating gate and erasing (deleting) electrons from the floating gate. The electrons are injected into the floating gate by a hot electron injection method (HEI) and are erased by a Fowler-Nordheim (F-N) tunneling method using an inter-gate insulating layer between the floating gate and the control gate.
A conventional flash memory device having a split gate with such characteristics is formed by the following method.
Referring to FIG. 1A, an isolation layer (not shown) is formed in a predetermined part of a semiconductor substrate 10 in order to define an active region 15. A gate oxide layer 20 and a polysilicon layer (not shown) for a floating gate electrode are deposited on the semiconductor substrate 10 in which the active region 15 is formed. A silicon nitride layer pattern (not shown) is formed using photolithography to expose a prearranged floating gate electrode region. A local oxide layer 30 is formed by oxidizing the polysilicon layer for a floating gate electrode, which is exposed by a silicon nitride layer pattern. Next, the silicon nitride layer pattern is removed. The polysilicon layer for a floating gate electrode is etched using the local oxide layer 30 as a mask, thus forming a floating gate pattern 25. Then, an inter-gate oxide layer 35 is formed on the surface of the gate oxide layer 20 and the floating gate pattern 25.
Referring to FIG. 1B, a polysilicon layer for a control gate electrode is deposited on the inter-gate oxide layer 35 and the local oxide layer 30. Next, a first mask pattern 45 is formed by standard photolithography so that the polysilicon layer for a control gate electrode can overlap with part of the upper part of the floating gate pattern 25 and both ends of the floating gate pattern 25. A control gate electrode 40 is defined by patterning the polysilicon layer for a control gate electrode using the first mask pattern 45.
Then, referring to FIG. 1C, the first mask pattern 45 is removed and a second mask pattern 50 is formed in order to define a source region. The second mask pattern 50 is formed so that part of the local oxide layer 30 is exposed. The local oxide layer 30 and the floating gate pattern 25 are etched using the second mask pattern 50, thus opening a prearranged source region and at the same time defining a floating gate electrode 25a. Next, a source region 55 is formed by implanting impurities into the exposed active region 15. Then, the second mask pattern 50 is removed.
Thus, in the flash memory device having a split gate, an active region is defined and then a local oxide layer is defined by a silicon nitride layer pattern using photolithography, thereby defining a floating gate electrode (floating gate pattern). At this point, misalignment between the floating gate electrode (floating gate pattern) and the active region may occur because the floating gate electrode is defined by additional photolithography when the active region is formed.
As described in connection with FIG. 1C, a final floating gate electrode is also defined by the second mask pattern 50 using photolithography. However, a highly integrated semiconductor has an increased chance of misalignment and a decreased photolithography margin when a narrow region, e.g. a mask pattern exposing a source region, is formed. As a result, the configuration of the floating gate electrodes facing each other may not be symmetrical, resulting in cell current differences, thus decreasing the uniformity of elements.
Although not described in connection with the above conventional device, the split gate flash memory device includes a source line connecting source regions. Since the source line is formed on the substrate by shaping a layer of material such as polysilicon, additional processes are required and the cell size is increased.